1. Field of Invention
This invention pertains to a protocol and a system for accessing one or more common memories over a common bus, and more particularly, to a common memory sharing system having a plurality of data processors, such as the type wherein each processor being provided to exchange data with an external computer or other data processing equipment.
2. Description of the Prior Art
It is frequently desirable for several data processors to exchange information through a common memory. (In this application the term "data processors" or "processors" refers to single chip microprocessors such as the common Z8000, or other similar devices) so that each can run in an asynchronous mode, i.e. independently of the others. For example, a high speed main frame computer may be tied to its peripherals and/or other main frame computer through a multi-processor system with separate processors being dedicated to the main frame or one of the peripherals. These processors enable data exchange between the various devices even though each may have its own coding scheme, and timing or protocol requirements. The microprocessors can be tied together through a set of common memories. However, most prior art configurations were rather slow because each program had to request access to one of the memories through a single memory control system, and then wait for an indetermined period until actual access for either a data reading or data writing operation was allowed.